Custom RISC V Processors design
Reduced instructions code, ad-hoc instruction implementation for security and differentiated embedded, IoT, AI/Edge computing applications.
Custom RISC V SoCs
World-class core + {IP design, 3rd party IP} integration covering a number of applications such as embedded, IoT and networking.
Proof of Concepts, Prototyping, HW platforms
Prototyping platforms design based on FPGA or ASIC cores for fast proof of concept evaluation or calibration.
Custom Machine Learning Accelerators in HW
Ad-hoc hardware implementations of neural networks provide security and optimal performance, power and area solutions. Our machine learning design flow guarantee quick turnaround times in synthesizable hardware implementations. As a result, you will get soft and hard IPs data bases of your neural network accelerator.
