Custom RISC V Processors design
Fully synthesizable FPGA (ASIC/Hard IP coming in 2021) and verified 32-bit core IP with RISC V ISA compliant. Including three core variants:
• DRL Lite core bare metal
• DRL Arduino for MCU applications
• DRL SoC Linux capable
Processor IP has rigorously verified to provide reliable, stable and FPGA/silicon proven solutions. DRL cores have competitive differentiation in terms of quick turn-around times for processor customization which provides impressive area and performance solutions
FPGA metrics for baseline configurations
• TBD
Machine Learning Accelerators
Our approach targets neural networks implementation in ad-hoc synthesizable hardware
ASIC/Hard IP roadmap:
